This document will provide a quick overview of the steps needed to perform a timing analysis in Quartus and calculate fMax, the maximum allowed clock frequency for the circuit. For more detailed instructions, see the PDF below.
To simulate a timing analysis, we need to create a register to register path for our circuit. This means the inputs and outputs need to be assigned to registers at the rising edge of each clock cycle, and then the output is assigned using assign.
In code:
module seqAdder (clock, A, B, C, sum);
input clock;
input [7:0] A,B,C;
output [9:0] sum;
// Create registers
reg [7:0] reg_A, reg_B, reg_C;
reg [9:0] reg_sum;
always @(posedge clock)
begin
reg_A <= A;
reg_B <= B;
reg_C <= C;
reg_sum <= reg_A + reg_B + reg_C;
end
assign sum = reg_sum;
endmodule
module multiplier(multiplicand, multiplier, clk, product);
input [31:0] multiplicand, multiplier;
input clk;
output [63:0] product;
reg [31:0] multiplicand_reg, multiplier_reg /* synthesis keep */;
reg [63:0] product_reg, product_output_reg /* synthesis keep */;
always @(multiplier_reg, multiplicand_reg) begin
product_reg = multiplier_reg * multiplicand_reg;
end
always @(posedge clk) begin
multiplicand_reg <= multiplicand;
multiplier_reg <= multiplier;
product_output_reg <= product_reg;
end
assign product = product_output_reg;
endmodule
Hit ctrl+L or Processing > Start Compilation. Then click Clocks under “TimeQuest Timing Analyzer” and right click on the clock signal and click “Report Timing…(In TimeQuest UI)”.
Choose the clock needed and leave everything else as defaults (your clock might be called “clk”, this is OK). Then click “Report Timing.”
A window with timings should come up, along with slack numbers (likely negative / red):
Click on “Path Summary” if it isn’t already visible (this is in the middle on the above screenshot). Look at the data arrival time (line 5). This is the amount of time the signal took to go from register to register in nanoseconds. Use this period to calculate the maximum clock frequency fMax allowed for this circuit (i.e. 1/(data arrival time)).