Follow these instructions to create and simulate a project in Quartus. Adapted from E15A lab by Erik Cheever.

Creating a New Project

1. Create a folder for files for this lab in a location of your choosing.

2. Start Quartus and select "New Project Wizard."

3. On the "Directory, Name, Top-Level Entity" page, choose the directory you just created and name the project. It is a good idea to name the project the same thing as your "top-level entity." Then hit "Next."

   

4. Select "Empty Project" and then hit "Next."

5. Hit "Next" on the "Add Files" screen.

6. On the next page ("Family, Device & Board Settings"), choose the "Board" tab and choose the "DE0-CV Development Board," and then hit "Next."

   

7. On the next page ("EDA Tool Settings"), under "Tool Type → Simulation" pick "ModelSim-Altera" for the "Tool name" and "Verilog HDL" for format. Then hit "Next."

8. Hit "Finish." Your project will then setup and launch.

Creating Your First Module

1. Create a new Verilog HDL file using "File → New" and select "Verilog HDL file."
2. Save the .v file using either "File - Save" or ctrl+S (you may have to enter some text to save it).
3. Populate your .v file with the code for the module.
4. Set the module as the "top level entity" using "Project → Set as Top-Level Entity."
5. Go to "Processing → Start → Analysis and Synthesis" (or ctrl+K). This will prepare your module for simulation.

Simulating Your Module

1. Go to "Tools → Options → EDA Tool Options" and set the ModelSim directory. (It should be something similar to what is shown in the screenshot below.)

   

2. Go to "File → New →Verification/Debugging Files → University Program VWF."

3. When the "Simulation Waveform Editor" window appears click "Edit → Insert → Node or Bus."