Announcements

• Lab 1 is due today
• I will be finished grading Homework 1 tomorrow
• Office hours: by appointment (email me if none of those times work)

Learning Objectives and Outcomes

In this lecture, you will...

• complete a short class reflection exercise
• listen to a short lecture on sequential modules in verilog
• work in small groups to implement a 2-bit comparator, a 4-channel multiplexer, and a 32 bit adder

By the end of this lecture, you should be able to...

• write and simulate a combinational or sequential module in verilog

In Class Work

Lecture 7 - Sequential in Verilog.pptx

introVerilog.pdf

Prepare for next class

Please complete the reading before the next class. Complete the participation activities as you go. If you aren't done after an hour, feel free to stop where you are (as long as I've seen you've made an effort, you'll get credit for participation). Sections marked "optional" will be covered during lecture or are there for your reference.