Types of assignment and types of circuits

When to use each of these for circuit type? (always, never, sometimes)

Scenario Combinational Sequential
assign use for one liners only for output (usually)
always whenever we want, but needed when we can’t just use assign w/ clock, registers
blocking assignment (=) always (e.g. multiplier) avoid
non-blocking assignment (<=) avoid always

Choosing Types of Assignment

How do we decide between using assign, blocking, or non-blocking?

Scenario When To Use
assign outside always block, not with regs
blocking assignment (=) when the order of execution matters
non-blocking assignment (<=) when the order of execution does NOT matter (except the timing, which is on a clock edge)

Further reading:

Wire vs. Reg

See wire vs. reg.

Scenario Wire Reg
Input yes no
Output yes yes
Left side in always no yes
Right side in always yes yes
Left side in assign yes no
Right side in assign yes yes

Resolving Common Verilog Errors/Warnings

Error/Warning Resolution Notes
Warning: inferring latches Make sure a register is always set for each path through the circuit in always block. One easy way is to initialize all registers of always block. Intel documentation, might cause ModelSim to give infinite loop (max iterations)
Error (10219): object on left-hand side of assignment must have a net type change left hand side to wire
Error (10170): "end" without "begin". add a begin
Error (10137): left-hand side of assignment must have a variable data type change left hand side to reg
Stuck at Vcc / Gnd don’t always need to resolve if intended means that it’s always 1 or always 0

Working with signed numbers in Verilog

(For signed multiplication and division, see relevant sections of textbook.)

Signed vs. unsigned is a convention.

Common mistakes: